Contemporary electronic design automation (EDA) tools in general and automatic test pattern generation (ATPG) in particular are capable of producing tests that offer high coverage of failures occurring in large and complex semiconductor digital designs. Notwithstanding the success of test compression, ATPG-produced test sets continue to grow at alarming rates. This is mainly caused by: 1) designs feature a large number of clock domains with staggeringly complex clocking schemes; 2) a typical test generation process for at-speed patterns includes a large number of steps, with all of them handling several clock sequences; 3) the ratios of gates and flip-flops are large and still increasing, but the number of I/O pins does not follow the continuing growth in the number of gates and flip-flops inside a chip; 4) tested circuits comprise logic of large combinational depths; 5) automatically generated register-transfer level (RTL) designs feature complex control logic circuits; and 6) a typical test set contains many long tail test patterns—although these patterns contain very few specified bits, their mutual conflicts effectively prevent compression-aware merging of test cubes.
Moreover, the gate level abstraction and traditional fault models (stuck-at, transition) are no longer sufficient to ensure high quality and low-DPM (defects per million) metrics for state-of-the-art digital circuits. As a result, the next generation tools are expected to target novel timing-related and actual-layout-related fault models and patterns, such as n-detect, embedded-multi-detect, or recently proposed cell-aware. Unfortunately, this trend leads to inflated test sets that require more storage than many external testers can provide. The test application time is an even more evident efficiency limiting and cost-increasing factor, which has become an unprecedented challenge in the testing of embedded systems, automotive electronics, or system-on-chip designs, to name just a few.
The disclosed technology relates to inserting conflict-reducing test points which can reduce test pattern counts. Traditionally, test point insertion techniques attempt to improve the fault detection likelihood while minimizing a necessary hardware real estate. They select internal lines in a circuit to subsequently add control points or observation points in order to activate (excite) faults or observe them, respectively. Identification of potential test point candidates is a complex problem because of several interacting factors. In general, optimal test point insertion for circuits with reconvergent fan-outs is an NP-complete problem and, hence, numerous empirical guidelines and approximate techniques have been proposed to identify suitable test points (control points and observation points) locations and improve the overall circuit testability.
Depending on how a test point is driven or observed, its insertion may require a few extra gates and wires routed to or from additional flip-flops to be included in scan chains. As it introduces area and performance penalty, the number of test points is usually limited. Furthermore, the identification of test points must be computationally inexpensive despite the structural complexity of large designs.
The first systematic TPI method was introduced in Briers, A. J. and Totton, K. A. E., “Random Pattern Testability By Fault Simulation”, Proceedings of the IEEE International Test Conference, ITC'86. 274-281, 1986, which is incorporated herein by reference. Simulations are used first to obtain profiles of fault propagation and correlations between internal signals. Test points are then inserted to break signal correlations.
Similarly, the technology disclosed in Iyengar, V. S. and Brand, D., “Synthesis Of Pseudorandom Pattern Testable Designs”, Proceedings of the IEEE International Test Conference, ITC'89. 501-508, 1989, which is incorporated herein by reference, employs fault simulation to identify gates that block fault propagation and inserts test points to regain successful propagation of fault effects.
A divide-and-conquer approach disclosed in Tamarapalli, N. and Rajski, J., “Constructive Multiphase Test Point Insertion For Scan-Based BIST”, Proceedings of the IEEE International Test Conference, ITC'96. 649-658, 1996, which is incorporated herein by reference, partitions the entire test into multiple phases. Within each phase, a group of test points is activated to maximize the fault coverage calculated over the set of still-undetected faults. A probabilistic fault simulation, which computes the impact of a new control point in the presence of the control points already selected, is used as a vehicle to select test points.
To avoid time-consuming simulations, other methods utilize the controllability and observability measures to identify the hard-to-control and hard-to-observe sectors of a circuit, at which test points are subsequently inserted. In particular, the schemes disclosed in Cheng, K.-T., and Lin, C.-J., “Timing-Driven Test Point Insertion For Full-Scan And Partial-Scan BIST”, Proceedings of the IEEE International Test Conference, ITC'95, 506-514, 1995 and Nakao, M., Hatayama, K., and Highasi, I., “Accelerated test points selection method for scan-based BIST”, Proceedings of the IEEE Asian Test Symposium, ATS'97, 359-364, 1997, which are incorporated herein by reference, use COP (Controllability Observability Program) estimates to extract testability data. Hybrid testability measures based on the SCOAP (Sandia Controllability/Observability Analysis Program) metrics, cost functions, a gradient-based method, or signal correlation are used as well to determine the best TP sites.
These conventional test point insertion techniques can improve the fault detection likelihood, but may not affect test pattern counts at all. As reported in Kumar, A., Rajski, J., Reddy, S. M., and Rinderknecht, T., “On the generation of compact deterministic test sets for BIST ready designs”, Proceedings of the IEEE Asian Test Symposium, ATS'13, 201-206, 2013, which is incorporated herein by reference, the reduction of these counts can average anywhere between 0 and 35%. Therefore, it is desirable to develop new test point insertion techniques that can reduce the volume of test data.